This invention relates to a method of making semi-conductor devices having fine dielectric element isolation regions.
A selective oxidation process has been widely used as useful means for making dielectric isolation regions. This process, for example, is disclosed by Japanese Patent Publication No. 17069/1975. FIGS. 1a to 1c shows the typical steps of making dielectric isolation regions for MOS IC semiconductor devices.
In FIG. 1a, silicon oxide film 11 is thermally grown on the surface of a silicon semiconductor substrate 10, and then a silicon nitride film 12 is formed on the surface of the oxide film 11 by a chemical vapor deposition (CVD) process.
Next, the silicon nitride film 12 is selectively etched off to form oxidation-resistant masks 14. Channel stop regions 13 are formed in the surface of the silicon substrate 10 by ion-implanting, e.g. boron atoms through the exposed surface of the oxide film 11 (see FIG. 1b).
Thereafter, with the oxidation-resistant masks 14, the structure obtained is heated in a wet oxygen atmosphere, so that thick field oxide regions 15 as an element isolation having a thickness of 300-1000 nm is formed (see FIG. 1c). After removing the oxidation-resistant mask 14, MOS transistor elements, for example, are formed in the active regions 16.
However, the conventional process described above has disadvantages in that the thermally grown oxide invades the silicon substrate under the oxidation-resistant masks 14 to form so-called bird's beak regions 17, making it difficult to accurately control the sizes of field regions 15 and active regions 16. Furthermore, during the heat oxidation process, the channel stop regions 13 widen through outer diffusion, so that the effective gate width of the MOS transisor is narrowed which degrades the transconductance (gm) of the MOS transistor. Therefore, it is difficult to miniaturize the sizes of active regions.